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MCP6V01/2/3
300 A, Auto-Zeroed Op Amps
Features
* High DC Precision: - VOS Drift: 50 nV/C (maximum) - VOS: 2 V (maximum) - AOL: 130 dB (minimum) - PSRR: 130 dB (minimum) - CMRR: 130 dB (minimum) - Eni: 2.5 VP-P (typical), f = 0.1 Hz to 10 Hz - Eni: 0.79 Vp-p (typical), f = 0.01 Hz to 1 Hz * Low Power and Supply Voltages: - IQ: 300 A/amplifier (typical) - Wide Supply Voltage Range: 1.8V to 5.5V * Easy to Use: - Rail-to-Rail Input/Output - Gain Bandwidth Product: 1.3 MHz (typical) - Unity Gain Stable - Available in Single and Dual - Single with Chip Select (CS): MCP6V03 * Extended Temperature Range: -40C to +125C
Description
The Microchip Technology Inc. MCP6V01/2/3 family of operational amplifiers has input offset voltage correction for very low offset and offset drift. These devices have a wide gain bandwidth product (1.3 MHz, typical) and strongly reject switching noise. They are unity gain stable, have no 1/f noise, and have good PSRR and CMRR. These products operate with a single supply voltage as low as 1.8V, while drawing 300 A/amplifier (typical) of quiescent current. The Microchip Technology Inc. MCP6V01/2/3 op amps are offered in single (MCP6V01), single with Chip Select (CS) (MCP6V03), and dual (MCP6V02). They are designed in an advanced CMOS process.
Package Types (top view)
MCP6V01 SOIC
NC 1 VIN- 2 VIN+ 3 VSS 4 8 NC 7 VDD 6 VOUT 5 NC
MCP6V01 2x3 TDFN *
NC 1 VIN- 2 VIN+ 3 VSS 4 EP 9 8 NC 7 VDD 6 VOUT 5 NC
Typical Applications
* * * * * Portable Instrumentation Sensor Conditioning Temperature Measurement DC Offset Correction Medical Instrumentation
MCP6V02 SOIC
VOUTA 1 VINA- 2 VINA+ 3 VSS 4 8 VDD VOUTA 7 VOUTB V - INA 6 VINB- V + INA 5 VINB+ V
SS
MCP6V02 4x4 DFN *
1 2 3 4 EP 9 8 VDD 7 VOUTB 6 VINB- 5 VINB+
Design Aids
* * * * * * SPICE Macro Models FilterLab(R) Software MindiTM Circuit Designer & Simulator Microchip Advanced Part Selector (MAPS) Analog Demonstration and Evaluation Boards Application Notes
MCP6V03 SOIC
NC 1 VIN- 2 VIN+ 3 VSS 4 8 CS 7 VDD 6 VOUT 5 NC
MCP6V03 2x3 TDFN *
NC 1 VIN- 2 VIN+ 3 VSS 4 EP 9 8 CS 7 VDD 6 VOUT 5 NC
Related Parts
* MCP6V06/7/8: Non-spread clock, lower noise
* Includes Exposed Thermal Pad (EP); see Table 3-1.
(c) 2008 Microchip Technology Inc.
DS22058C-page 1
MCP6V01/2/3
Typical Application Circuit
VIN R1 R2 C2 3 k MCP6V01 MCP6XXX R3 VOUT
R2 VDD/2
Offset Voltage Correction for Power Driver
DS22058C-page 2
(c) 2008 Microchip Technology Inc.
MCP6V01/2/3
1.0
1.1
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. See Section 4.2.1 "Rail-to-Rail Inputs".
VDD - VSS .......................................................................6.5V Current at Input Pins ....................................................2 mA Analog Inputs (VIN+ and VIN-) ... VSS - 1.0V to VDD+1.0V All other Inputs and Outputs ............ VSS - 0.3V to VDD+0.3V Difference Input voltage ...................................... |VDD - VSS| Output Short Circuit Current ................................ Continuous Current at Output and Supply Pins ............................30 mA Storage Temperature ...................................-65C to +150C Max. Junction Temperature ........................................ +150C ESD protection on all pins (HBM, MM) ................ 4 kV, 300V
1.2
Specifications
DC ELECTRICAL SPECIFICATIONS
TABLE 1-1:
Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 20 k to VL, and CS = GND (refer to Figure 1-5 and Figure 1-6).
Parameters
Input Offset Input Offset Voltage Input Offset Voltage Drift with Temperature (linear Temp. Co.) Input Offset Voltage Quadratic Temp. Co. Power Supply Rejection Input Bias Current and Impedance Input Bias Current Input Bias Current across Temperature Input Offset Current Input Offset Current across Temperature Common Mode Input Impedance Differential Input Impedance Common Mode Common-Mode Input Voltage Range Common-Mode Rejection
Sym
VOS TC1 TC2 PSRR IB IB IB IOS IOS IOS ZCM ZDIFF VCMR CMRR
Min
-2.0 -50 -- 130 -- -- -- -- -- -1000 -- -- VSS - 0.20 130
Typ
-- -- 0.1 143 1 60 600 -30 -50 -75 1013||6 1013||6 -- 142
Max
+2.0 +50 -- -- -- -- 5000 -- -- 1000 -- -- VDD + 0.20 --
Units
V nV/C
Conditions
TA = +25C (Note 1) TA = -40 to +125C (Note 1) (Note 1)
nV/C2 TA = -40 to +125C dB pA pA pA pA pA pA ||pF ||pF V dB (Note 2) VDD = 1.8V, VCM = -0.2V to 2.0V (Note 1, Note 2) VDD = 5.5V, VCM = -0.2V to 5.7V (Note 1, Note 2) VDD = 1.8V, VOUT = 0.2V to 1.6V (Note 1) VDD = 5.5V, VOUT = 0.2V to 5.3V (Note 1) TA = +85C TA = +125C TA = +85C TA = +125C
CMRR
140
152
--
dB
Open-Loop Gain DC Open-Loop Gain (large signal) AOL AOL Note 1: 2: 130 140 145 156 -- -- dB dB
Set by design and characterization. Due to thermal junction and other effects in the production environment, these parts can only be screened in production (except TC1; see Appendix B: "Offset Related Test Screens"). Figure 2-18 shows how VCMR changed across temperature for the first three production lots.
(c) 2008 Microchip Technology Inc.
DS22058C-page 3
MCP6V01/2/3
TABLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 20 k to VL, and CS = GND (refer to Figure 1-5 and Figure 1-6).
Parameters
Output Maximum Output Voltage Swing Output Short Circuit Current Power Supply Supply Voltage Quiescent Current per amplifier POR Trip Voltage Note 1: 2:
Sym
VOL, VOH ISC ISC VDD IQ VPOR
Min
VSS + 15 -- -- 1.8 200 1.15
Typ
-- 7 22 -- 300 --
Max
VDD - 15 -- -- 5.5 400 1.65
Units
mV mA mA V A V IO = 0
Conditions
G = +2, 0.5V input overdrive VDD = 1.8V VDD = 5.5V
Set by design and characterization. Due to thermal junction and other effects in the production environment, these parts can only be screened in production (except TC1; see Appendix B: "Offset Related Test Screens"). Figure 2-18 shows how VCMR changed across temperature for the first three production lots.
TABLE 1-2:
AC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 20 k to VL, CL = 60 pF, and CS = GND (refer to Figure 1-5 and Figure 1-6).
Parameters
Amplifier AC Response Gain Bandwidth Product Slew Rate Phase Margin Amplifier Noise Response Input Noise Voltage Input Noise Voltage Density Input Noise Current Density Amplifier Distortion (Note 1) Intermodulation Distortion (AC) Amplifier Step Response Start Up Time Offset Correction Settling Time Output Overdrive Recovery Time Note 1: 2:
Sym
GBWP SR PM Eni Eni eni eni ini IMD IMD tSTR tSTL tODR
Min
-- -- -- -- -- -- -- -- -- -- -- -- --
Typ
1.3 0.5 65 0.79 2.5 120 45 0.6 <1 <1 500 300 100
Max
-- -- -- -- -- -- -- -- -- -- -- -- --
Units
MHz V/s VP-P VP-P G = +1
Conditions
f = 0.01 Hz to 1 Hz f = 0.1 Hz to 10 Hz
nV/Hz f < 2.5 kHz nV/Hz f = 100 kHz fA/Hz VPK VPK s s s VCM tone = 50 mVPK at 1 kHz, GN = 1, VDD = 1.8V VCM tone = 50 mVPK at 1 kHz, GN = 1, VDD = 5.5V VOS within 50 V of its final value G = +1, VIN step of 2V, VOS within 50 V of its final value G = -100, 0.5V input overdrive to VDD/2, VIN 50% point to VOUT 90% point (Note 2)
These parameters were characterized using the circuit in Figure 1-7. Figure 2-37 and Figure 2-38 show both an IMD tone at DC and a residual tone at1 kHz; all other IMD and clock tones are spread by the randomization circuitry. tODR includes some uncertainty due to clock edge timing.
DS22058C-page 4
(c) 2008 Microchip Technology Inc.
MCP6V01/2/3
TABLE 1-3: DIGITAL ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 20 k to VL, CL = 60 pF, and CS = GND (refer to Figure 1-5 and Figure 1-6).
Parameters
CS Pull-Down Resistor (MCP6V03) CS Pull-Down Resistor CS Low Specifications (MCP6V03) CS Logic Threshold, Low CS Input Current, Low CS High Specifications (MCP6V03) CS Logic Threshold, High CS Input Current, High CS Input High, GND Current per amplifier
Sym
RPD VIL ICSL VIH ICSH ISS ISS
Min
3 VSS --
Typ
5 -- 5
Max
-- 0.3VDD --
Units
M V pA CS = VSS
Conditions
0.7VDD -- -- -- --
-- VDD/RPD -0.7 -2.3 20
VDD -- -- -- --
V pA A A pA CS = VDD CS = VDD, VDD = 1.8V CS = VDD, VDD = 5.5V CS = VDD CS Low = VSS+0.3 V, G = +1 V/V, VOUT = 0.9 VDD/2 CS High = VDD - 0.3 V, G = +1 V/V, VOUT = 0.1 VDD/2
Amplifier Output Leakage, CS High IO_LEAK CS Dynamic Specifications (MCP6V03) CS Low to Amplifier Output On Turn-on Time CS High to Amplifier Output High-Z Internal Hysteresis tON tOFF VHYST
-- -- --
11 10 0.25
100 -- --
s s V
TABLE 1-4:
TEMPERATURE SPECIFICATIONS
Parameters Sym
TA TA TA JA JA JA
Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VDD = +1.8V to +5.5V, VSS = GND.
Min
-40 -40 -65 -- -- --
Typ
-- -- -- 41 44 150
Max
+125 +125 +150 -- -- --
Units
C C C C/W C/W C/W (Note 2) (Note 1)
Conditions
Temperature Ranges
Specified Temperature Range Operating Temperature Range Storage Temperature Range
Thermal Package Resistances
Thermal Resistance, 8L-2x3 TDFN Thermal Resistance, 8L-4x4 DFN Thermal Resistance, 8L-SOIC Note 1: 2:
Operation must not cause TJ to exceed Maximum Junction Temperature specification (150C). Measured on a standard JC51-7, four layer printed circuit board with ground plane and vias.
(c) 2008 Microchip Technology Inc.
DS22058C-page 5
MCP6V01/2/3
1.3 Timing Diagrams
1.8V tSTR VOS 1.8V to 5.5V VOS + 50 V VOS - 50 V VIN RN
1.4
Test Circuits
VDD 0V
The circuits used for the DC and AC tests are shown in Figure 1-5 and Figure 1-6. Lay the bypass capacitors out as discussed in Section 4.3.8 "Supply Bypassing and Filtering". RN is equal to the parallel combination of RF and RG to minimize bias current effects. VDD 1 F RISO 100 nF RG RF CL RL VL VOUT
FIGURE 1-1:
VIN
Amplifier Start Up.
MCP6V0X VDD/3
tSTL VOS
VOS + 50 V VOS + 50 V
FIGURE 1-5: AC and DC Test Circuit for Most Non-Inverting Gain Conditions.
VDD 1 F RISO 100 nF RG RF CL RL VL VOUT
FIGURE 1-2: Time.
VIN tODR VDD
Offset Correction Settling
VDD/3 RN MCP6V0X VIN
tODR VOUT VDD/2 VSS
FIGURE 1-6: AC and DC Test Circuit for Most Inverting Gain Conditions.
The circuit in Figure 1-7 tests the op amp input's dynamic behavior (i.e., IMD, tSTR, tSTL and tODR). The potentiometer balances the resistor network (VOUT should equal VREF at DC). The op amp's common mode input voltage is VCM = VIN/2. The error at the input (VERR) appears at VOUT with a noise gain of 10 V/V. 20.0 k 20.0 k 50 0.1% 0.1% 25 turn High-Z 2.49 k 2.49 k 1 A (typical) VDD
FIGURE 1-3:
CS tON VOUT IDD High-Z 1 A (typical) VIL
Output Overdrive Recovery.
VIH tOFF
VREF
300 A (typical) 300 A (typical) 5 pA (typical)
1 F RISO 100 nF CL VL VOUT RL
ISS -2 A (typical) ICS V /5 M DD (typical)
-2 A (typical) VDD/5 M (typical)
VIN
MCP6V0X
20.0 k 20.0 k 24.9 0.1% 0.1%
FIGURE 1-4:
Chip Select (MCP6V03).
FIGURE 1-7: Input Behavior.
Test Circuit for Dynamic
DS22058C-page 6
(c) 2008 Microchip Technology Inc.
MCP6V01/2/3
2.0
Note:
TYPICAL PERFORMANCE CURVES
The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 20 k to VL, CL = 60 pF, and CS = GND.
2.1
DC Input Precision
20% 18% 16% 14% 12% 10% 8% 6% 4% 2% 0%
78 Samples TA = +25C VDD = 1.8V and 5.5V Soldered on PCB
4 Input Offset Voltage (V) 3 2 1 0 -1 -2 -3 -4
+125C +85C +25C -40C
Percentage of Occurrences
VCM = VCMR_L Representative Part
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
Input Offset Voltage (V)
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 Power Supply Voltage (V)
FIGURE 2-1:
Input Offset Voltage.
FIGURE 2-4: Input Offset Voltage vs. Power Supply Voltage with VCM = VCMR_L.
4 Input Offset Voltage (V) 3 2 1 0 -1 -2 -3 -4
+125C +85C +25C -40C VCM = VCMR_H Representative Part
22% 20% 18% 16% 14% 12% 10% 8% 6% 4% 2% 0%
Percentage of Occurrences
78 Samples VDD = 1.8V and 5.5V Soldered on PCB
-50
-40
-30
-20
-10
0
10
20
30
40
50
Input Offset Voltage Drift; TC1 (nV/C)
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 Power Supply Voltage (V)
FIGURE 2-2:
Input Offset Voltage Drift.
FIGURE 2-5: Input Offset Voltage vs. Power Supply Voltage with VCM = VCMR_H.
4 Input Offset Voltage (V) 3 2 1 0 -1 -2 -3 -4 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Output Voltage (V)
Representative Part
Percentage of Occurrences
22% 20% 18% 16% 14% 12% 10% 8% 6% 4% 2% 0%
78 Samples VDD = 1.8V and 5.5V Soldered on PCB
VDD = 1.8V
VDD = 5.5V
-0.4
-0.3
-0.2
-0.1
0.1
0.2
0.3
0.0
Input Offset Voltage's Quadratic Temp Co; 2 TC2 (nV/C )
FIGURE 2-3: Input Offset Voltage Quadratic Temp Co.
(c) 2008 Microchip Technology Inc.
0.4
FIGURE 2-6: Output Voltage.
Input Offset Voltage vs.
DS22058C-page 7
MCP6V01/2/3
Note: Unless otherwise indicated, TA = +25C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 20 k to VL, CL = 60 pF, and CS = GND.
4 Input Offset Voltage (V) 3 2 1 0 -1 -2 -3 -4 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 Input Common Mode Voltage (V)
+125C +85C +25C -40C
Percentage of Occurrences
VDD = 1.8V Representative Part
14% 12% 10% 8% 6% 4% 2% 0%
40 Samples TA = +25C Soldered on PCB
-0.3
-0.2
-0.1
0.0
0.1
0.2
1/PSRR (V/V)
FIGURE 2-7: Input Offset Voltage vs. Common Mode Voltage with VDD = 1.8V.
4 Input Offset Voltage (V) 3 2 1 0 -1 -2 -3 -4 0.5 -0.5 5.0 0.0 2.5 1.0 1.5 2.0 3.0 3.5 4.0 4.5 5.5 6.0 Input Common Mode Voltage (V)
VDD = 5.5V Representative Part
FIGURE 2-10:
PSRR.
Percentage of Occurrences
+125C +85C +25C -40C
55% 50% 45% 40% 35% 30% 25% 20% 15% 10% 5% 0%
40 Samples TA = +25C VDD = 5.5V
VDD = 1.8V
-0.3
-0.2
-0.1
0.0
0.1
0.2
1/AOL (V/V)
FIGURE 2-8: Input Offset Voltage vs. Common Mode Voltage with VDD = 5.5V.
35% 30% 25% 20% 15% 10% 5% 0% -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 1/CMRR (V/V)
VDD = 1.8V
FIGURE 2-11:
DC Open-Loop Gain.
Percentage of Occurrences
CMRR, PSRR (dB)
39 Samples TA = +25C Soldered on PCB
160 155
VDD = 5.5V
VDD = 5.5V VDD = 1.8V
150 145 140 135 130 125 120 -50 -25 0 25 50 75 Ambient Temperature (C) 100 125
PSRR CMRR
FIGURE 2-9:
CMRR.
FIGURE 2-12: CMRR and PSRR vs. Ambient Temperature.
DS22058C-page 8
(c) 2008 Microchip Technology Inc.
0.3
0.3
MCP6V01/2/3
Note: Unless otherwise indicated, TA = +25C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 20 k to VL, CL = 60 pF, and CS = GND.
160 DC Open-Loop Gain (dB) 155 150 145 140 135 130 125 120 -50 -25 0 25 50 75 Ambient Temperature (C) 100 125
VDD = 5.5V VDD = 1.8V
1,000 Input Bias, Offset Currents (pA)
VDD = 5.5V
100
-IOS
10
IB
1 25 35 45 55 65 75 85 95 105 115 125 Ambient Temperature (C)
FIGURE 2-13: DC Open-Loop Gain vs. Ambient Temperature.
FIGURE 2-16: Input Bias and Offset Currents vs. Ambient Temperature with VDD = +5.5V.
1.E-02 10m 1m 1.E-03 100 1.E-04 10 1.E-05 1 1.E-06 100n 1.E-07 10n 1.E-08 1n 1.E-09 100p 1.E-10 10p 1.E-11 1p 1.E-12
160 140 120 100 80 60 40 20 0 -20 -40 -60 -0.5
Input Bias, Offset Currents (pA)
IB
Input Current Magnitude (A)
TA = +85C VDD = 5.5V
IOS
+125C +85C +25C -40C
0.0
3.5
4.0
4.5
0.5
1.0
1.5
2.0
2.5
3.0
5.0
5.5
6.0
Common Mode Input Voltage (V)
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 Input Voltage (V)
FIGURE 2-14: Input Bias and Offset Currents vs. Common Mode Input Voltage with TA = +85C.
1600 1400 1200 1000 800 600 400 200 0 -200 -400 -0.5 Input Bias, Offset Currents (pA)
TA = +125C VDD = 5.5V IB
FIGURE 2-17: Input Bias Current vs. Input Voltage (below VSS).
IOS
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Common Mode Input Voltage (V)
FIGURE 2-15: Input Bias and Offset Currents vs. Common Mode Input Voltage with TA = +125C.
(c) 2008 Microchip Technology Inc.
6.0
DS22058C-page 9
MCP6V01/2/3
Note: Unless otherwise indicated, TA = +25C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 20 k to VL, CL = 60 pF, and CS = GND.
2.2
Other DC Voltages and Currents
0.05 0.00 -0.05 -0.10 -0.15 -0.20 -0.25 -0.30 -0.35 -50 -25 0 25 50 75 100 Ambient Temperature (C) 125
Upper ( VDD - VCMR) Lower (VCMR - VSS)
Input Common Mode Voltage Headroom (V)
Output Short Circuit Current (mA)
3 Lots
40 30 20 10 0 -10 -20 -30 -40 0.0
-40C +25C +85C +125C
+125C +85C +25C -40C
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5 5.5
6.0 6.0
Power Supply Voltage (V)
FIGURE 2-18: Input Common Mode Voltage Headroom (Range) vs. Ambient Temperature.
1000 Output Voltage Headroom (mV)
FIGURE 2-21: Output Short Circuit Current vs. Power Supply Voltage.
450 400 Supply Current (A)
VDD = 5.5V
350 300 250 200 150 100 50 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
+125C +85C +25C -40C
100
VDD - VOH
VDD = 1.8V
VOL - VSS
0.1
1 Output Current Magnitude (mA)
10
Power Supply Voltage (V)
FIGURE 2-19: Output Voltage Headroom vs. Output Current.
12 11 10 9 8 7 6 5 4 3 2 1 0
FIGURE 2-22: Supply Voltage.
30% 25% 20% 15% 10% 5% 0%
93 Samples 3 Lots TA = +25C
Supply Current vs. Power
RL = 20 k
VDD = 5.5V VOL - VSS VDD - VOH
VDD = 1.8V
Percentage of Occurrences
Output Headroom (mV)
1.5
1.4
1.1
1.2
1.3
1.6
-50
-25
0 25 50 75 Ambient Temperature (C)
100
125
POR Trip Voltage (V)
FIGURE 2-20: Output Voltage Headroom vs. Ambient Temperature.
FIGURE 2-23: Voltage.
Power On Reset Trip
DS22058C-page 10
(c) 2008 Microchip Technology Inc.
1.7
6.5
10
6.5
MCP6V01/2/3
Note: Unless otherwise indicated, TA = +25C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 20 k to VL, CL = 60 pF, and CS = GND.
1.8 POR Trip Voltage (V) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -50 -25 0 25 50 75 Ambient Temperature (C) 100 125
FIGURE 2-24: Power On Reset Voltage vs. Ambient Temperature.
(c) 2008 Microchip Technology Inc.
DS22058C-page 11
MCP6V01/2/3
Note: Unless otherwise indicated, TA = +25C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 20 k to VL, CL = 60 pF, and CS = GND.
2.3
Frequency Response
110 100 90 80 70 60 50 40 30 20 10 0 10 1.E+01 1.8 Gain Bandwidth Product (MHz) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 100 1.E+02 1k 10k 1.E+03 1.E+04 Frequency (Hz) 100k 1.E+05 1M 1.E+06 -50 -25 0 25 50 75 100 Ambient Temperature (C)
PM GBWP VDD = 5.5V
130 120 100 90 80 70
VDD = 1.8V
CMRR, PSRR (dB)
CMRR
PSRR+ PSRR-
60 50 40 125
FIGURE 2-25: Frequency.
60 50 Open-Loop Gain (dB) 40 30 20 10 0 -10 -20 -30 1k 1.E+03
CMRR and PSRR vs.
FIGURE 2-28: Gain Bandwidth Product and Phase Margin vs. Ambient Temperature.
1.8 Gain Bandwidth Product (MHz) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0
PM VDD = 1.8V VDD = 5.5V
VDD = 1.8V CL = 60 pF
0 -30 -60 Open-Loop Phase () -90 -120 -150 -180 -210 -240
GBWP
130 120 100 90 80 70 60 50 40 Phase Margin () Phase Margin () 110
AOL | AOL |
10k 100k 1M 1.E+04 1.E+05 1.E+06 Frequency (Hz)
-270 10M 1.E+07
FIGURE 2-26: Open-Loop Gain vs. Frequency with VDD = 1.8V.
FIGURE 2-29: Gain Bandwidth Product and Phase Margin vs. Common Mode Input Voltage.
0
60 50 Open-Loop Gain (dB) 40 30 20 10 0 -10 -20 -30 1k 1.E+03
| AOL |
Gain Bandwidth Product (MHz)
VDD = 5.5V CL = 60 pF
1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0
Open-Loop Phase ()
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Common Mode Input Voltage (V)
GBWP
130 120 110 100
VDD = 1.8V VDD = 5.5V
-30 -60 -90 -120 -150 -180 -210 -240
AOL
90 80 70 60 50 40
PM
10k 100k 1M 1.E+04 1.E+05 1.E+06 Frequency (Hz)
-270 10M 1.E+07
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Output Voltage (V)
FIGURE 2-27: Open-Loop Gain vs. Frequency with VDD = 5.5V.
FIGURE 2-30: Gain Bandwidth Product and Phase Margin vs. Output Voltage.
DS22058C-page 12
(c) 2008 Microchip Technology Inc.
Phase Margin ()
110
MCP6V01/2/3
Note: Unless otherwise indicated, TA = +25C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 20 k to VL, CL = 60 pF, and CS = GND.
10k 1.E+04
Open-Loop Output Impedance ( )
100
VDD = 1.8V
90 Channel-to-Channel Separation (dB) 80 70 60 50 40 30 20 10 0 100k 1.E+05
VDD = 1.8V VDD = 5.5V
RTI
1k 1.E+03 100 1.E+02 10 1.E+01 1 1.E+00 100k 1.0E+05
G = 1 V/V G = 10 V/V G = 100 V/V
1M 10M 1.0E+06 1.0E+07 Frequency (Hz)
100M 1.0E+08
1M 1.E+06 Frequency (Hz)
10M 1.E+07
FIGURE 2-31: Closed-Loop Output Impedance vs. Frequency with VDD = 1.8V.
Open-Loop Output Impedance ( ) 1.E+04 10k
FIGURE 2-33: Channel-to-Channel Separation vs. Frequency.
10 Maximum Output Voltage Swing (V P-P )
VDD = 5.5V
VDD = 5.5V
1k 1.E+03 100 1.E+02 10 1.E+01 1 1.E+00 100k 1.0E+05
G = 1 V/V G = 10 V/V G = 100 V/V
1
VDD = 1.8V
1M 10M 1.0E+06 1.0E+07 Frequency (Hz)
100M 1.0E+08
0.1 1k 1.E+03
10k 100k 1.E+04 1.E+05 Frequency (Hz)
1M 1.E+06
FIGURE 2-32: Closed-Loop Output Impedance vs. Frequency with VDD = 5.5V.
FIGURE 2-34: Maximum Output Voltage Swing vs. Frequency.
(c) 2008 Microchip Technology Inc.
DS22058C-page 13
MCP6V01/2/3
Note: Unless otherwise indicated, TA = +25C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 20 k to VL, CL = 60 pF, and CS = GND.
2.4
Input Noise Voltage Density; eni (nV/Hz)
Input Noise and Distortion
1000 1000 IMD Spectrum, RTI (VPK) Input Noise Voltage; Eni (V P-P ) 100
IMD tone at DC
GDM = 1 V/V VDD tone = 50 mVP-P, f = 1 kHz 1 kHz tone
VDD = 5.5V eni
100
100
10
VDD = 1.8V
VDD = 1.8V Eni(0 Hz to f)
VDD = 5.5V
10 10 1.E+01
100 1k 10k 1.E+02 1.E+03 1.E+04 Frequency (Hz)
10 100k 1.E+05
1 100 1.E+02
1k 10k 1.E+03 1.E+04 Frequency (Hz)
100k 1.E+05
FIGURE 2-35: vs. Frequency.
Input Noise Voltage Density
FIGURE 2-38: Inter-Modulation Distortion vs. Frequency with VDD Disturbance (see Figure 1-7).
VDD = 1.8V
Input Noise Voltage Density (nV/Hz)
160 140 120 100 80 60 40 20 0 0.0 2.5 3.5 4.5 -0.5 5.5 0.5 1.0 1.5 2.0 3.0 4.0 5.0 6.0 Common Mode Input Voltage (V)
VDD = 1.8V VDD = 5.5V
Input Noise Voltage; eni(t) (0.5 V/div)
NPBW = 10 Hz
NPBW = 1 Hz
0
10
20
30
40
50 60 t (s)
70
80
90
100
FIGURE 2-36: Input Noise Voltage Density vs. Input Common Mode Voltage.
100 IMD Spectrum, RTI (VPK)
FIGURE 2-39: Input Noise vs. Time with 1 Hz and 10 Hz Filters and VDD =1.8V.
VDD = 5.5V
10
residual 1 kHz tone
Input Noise Voltage; eni(t) (0.5 V/div)
IMD tone at DC
GDM = 1 V/V VCM tone = 50 mVPK, f = 1 kHz
NPBW = 10 Hz
VDD = 1.8V VDD = 5.5V
1 100 1.E+02
NPBW = 1 Hz
1k 10k 1.E+03 1.E+04 Frequency (Hz)
100k 1.E+05
0
10
20
30
40
50 60 t (s)
70
80
90
100
FIGURE 2-37: Inter-Modulation Distortion vs. Frequency with VCM Disturbance (see Figure 1-7).
FIGURE 2-40: Input Noise vs. Time with 1 Hz and 10 Hz Filters and VDD =5.5V.
DS22058C-page 14
(c) 2008 Microchip Technology Inc.
MCP6V01/2/3
Note: Unless otherwise indicated, TA = +25C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 20 k to VL, CL = 60 pF, and CS = GND.
2.5
5 4 3 2 1 0 -1 -2 -3 -4 -5 0
Time Response
70 65 60 55 50 45 40 35 30 25 20 80 100 120 140 160 180 Time (s)
Temperature increased by using heat gun for 8 seconds.
VDD = 5.5V G=1
VOS
20
40
60
PCB Temperature (C)
TPCB
Output Voltage (10 mV/div) 0
Input Offset Voltage (V)
2
4
6
8
10 12 Time (s)
14
16
18
20
FIGURE 2-41: Input Offset Voltage vs. Time with Temperature Change.
10 8 Input Offset Voltage (mV) 6 4 2 0 -2 -4 -6 -8 -10 0.0 0.2 0.4 0.6 0.8 1.0 s/div) 1.6 1.8 2.0 Time (200 1.2 1.4
VOS
FIGURE 2-44: Step Response.
5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 5 10
Non-inverting Small Signal
POR Trip Point VDD
5.0 4.5 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0
Output Voltage (V)
VDD = 5.5V G=1
4.0
Power Supply Voltage (V)
15
20 25 30 Time (s)
35
40
45
50
FIGURE 2-42: Input Offset Voltage vs. Time at Power Up.
7 Input, Output Voltages (V) 6 5 4 3 2 1 0 -1 0 1 2 3 4 5 6 Time (ms) 7 8 9 10
VOUT VIN
FIGURE 2-45: Step Response.
Non-inverting Large Signal
Output Voltage (10 mV/div)
VDD = 5.5V G=1
VDD = 5.5V G = -1
0
1
2
3
4
5 6 Time (s)
7
8
9
10
FIGURE 2-43: The MCP6V01/2/3 family shows no input phase reversal with overdrive.
FIGURE 2-46: Response.
Inverting Small Signal Step
(c) 2008 Microchip Technology Inc.
DS22058C-page 15
MCP6V01/2/3
Note: Unless otherwise indicated, TA = +25C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 20 k to VL, CL = 60 pF, and CS = GND.
6.0
VDD = 5.5V G = -1
5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 5 10 15
6 Input Voltage x G (V/V)
G VIN VOUT
5.0 Output Voltage (V) 4.0 3.0 2.0 1.0 0.0
5 4 3 2
Output Voltage (V)
VOUT
G VIN
VDD = 5.5V G = -100 V/V 0.5V Overdrive
1 0 -1
20 25 30 Time (s)
35
40
45
50
-1.0 Time (50 s/div)
FIGURE 2-47: Response.
0.9 0.8 Slew Rate (V/s) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 -50 -25
Falling Edge
Inverting Large Signal Step
FIGURE 2-49: Output Overdrive Recovery vs. Time with G = -100 V/V.
1000
Overdrive Recovery Time (s)
VDD = 5.5V Rising Edge
0.5V Output Overdrive
100
VDD = 5.5V tODR, high
VDD = 1.8V
10
tODR, low VDD = 1.8V
1 1 10 100 Inverting Gain Magnitude (V/V) 1000
0 25 50 75 Ambient Temperature (C)
100
125
FIGURE 2-48: Temperature.
Slew Rate vs. Ambient
FIGURE 2-50: Output Overdrive Recovery Time vs. Inverting Gain.
DS22058C-page 16
(c) 2008 Microchip Technology Inc.
MCP6V01/2/3
Note: Unless otherwise indicated, TA = +25C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 20 k to VL, CL = 60 pF, and CS = GND.
2.6
1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0
Chip Select Response (MCP6V03 only)
1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0
Chip Select Current (A)
1.5
2.0
2.5 3.0 3.5 4.0 4.5 Power Supply Voltage (V)
5.0
5.5
Chip Select Current (A)
CS = VDD
VDD = 5.5V
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Chip Select Voltage (V)
FIGURE 2-51: Chip Select Current vs. Power Supply Voltage.
400 Power Supply Current (A) 350 300 250 200 150 100 50 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 Chip Select Voltage (V) 1.6 1.8
Hysteresis Op Amp turns on here Op Amp turns off here
FIGURE 2-54: Select Voltage.
1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6
Chip Select Current vs. Chip
Output Voltage (V)
VDD = 1.8V G=1 VIN = 0.9V VL = 0V
VOUT On
VOUT Off VDD = 1.8V G = +1 V/V VIN= VDD RL = 10 k tied to VDD/2
VOUT Off
CS
Time (5 s/div)
FIGURE 2-52: Power Supply Current vs. Chip Select Voltage with VDD = 1.8V.
600 Power Supply Current (A) 500 400 300 200 100 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Chip Select Voltage (V)
Op Amp turns on here Op Amp turns off here VDD = 5.5V G=1 VIN = 2.75V VL = 0V
FIGURE 2-55: Chip Select Voltage, Output Voltage vs. Time with VDD = 1.8V.
5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 0 39 36 33 30 27 24 21 18 15 12 9 6 3 0
VOUT On
Output Voltage (V)
VOUT Off VDD = 5.5V G = +1 V/V VIN= VDD RL = 10 k tied to VDD/2
VOUT Off
Hysteresis
CS
5
10 15 20 25 30 35 40 45 50 Time (5 s/div)
FIGURE 2-53: Power Supply Current vs. Chip Select Voltage with VDD = 5.5V.
FIGURE 2-56: Chip Select Voltage, Output Voltage vs. Time with VDD = 5.5V.
(c) 2008 Microchip Technology Inc.
DS22058C-page 17
Chip Select Voltage (V)
Chip Select Voltage (V)
12 11 10 9 8 7 6 5 4 3 2 1 0
MCP6V01/2/3
Note: Unless otherwise indicated, TA = +25C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 20 k to VL, CL = 60 pF, and CS = GND.
70% Relative Chip Select Logic Levels; Low and High ( ) Pull-down Resistor (M) 65% 60% 55% 50% 45% 40% 35% 30% -50 -25 0 25 50 75 100 Ambient Temperature (C) 125
VIL/VDD VDD = 1.8V VIH/VDD VDD = 5.5V
7 6 5 4 3 2 1 0 -50 -25 0 25 50 75 Ambient Temperature (C) 100 125
FIGURE 2-57: Chip Select Relative Logic Thresholds vs. Ambient Temperature.
0.40 Chip Select Hysteresis (V) 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 -50 -25 0 25 50 75 Ambient Temperature (C) 100 125
VDD = 1.8V VDD = 5.5V
FIGURE 2-60: Chip Select's Pull-down Resistor (RPD) vs. Ambient Temperature.
2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0
CS = VDD Representative Part
+125C +85C +25C -40C
Power Supply Current (A)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Power Supply Voltage (V)
FIGURE 2-58:
16 Chip Select Turn On Time (s) 14 12 10 8 6 4 2 0 -50 -25
Chip Select Hysteresis.
FIGURE 2-61: Quiescent Current in Shutdown vs. Power Supply Voltage.
VDD = 5.5V
VDD = 1.8V
0 25 50 75 Ambient Temperature (C)
100
125
FIGURE 2-59: Chip Select Turn On Time vs. Ambient Temperature.
DS22058C-page 18
(c) 2008 Microchip Technology Inc.
6.5
MCP6V01/2/3
3.0 PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
MCP6V01 TDFN 6 2 3 4 -- -- -- 7 -- 1, 5, 8 9
PIN FUNCTION TABLE
MCP6V02 DFN 1 2 3 4 5 6 7 8 -- -- 9 SOIC 1 2 3 4 5 6 7 8 -- -- -- MCP6V03 TDFN 6 2 3 4 -- -- -- 7 -- 1, 5, 8 9 SOIC 6 2 3 4 -- -- -- 7 8 1, 5 -- SOIC 6 2 3 4 -- -- -- 7 -- 1, 5, 8 -- Symbol VOUT, VOUTA VIN-, VINA- VIN+, VINA+ VSS VINB+ VINB- VOUTB VDD CS NC EP Description Output (op amp A) Inverting Input (op amp A) Non-inverting Input (op amp A) Negative Power Supply Non-inverting Input (op amp B) Inverting Input (op amp B) Output (op amp B) Positive Power Supply Chip Select (op amp A) No Internal Connection Exposed Thermal Pad (EP); must be connected to VSS
3.1
Analog Outputs
3.4
Chip Select (CS) Digital Input
The analog output pins (VOUT) are low-impedance voltage sources.
This pin (CS) is a CMOS, Schmitt-triggered input that places the MCP6V03 op amps into a low power mode of operation.
3.2
Analog Inputs
The non-inverting and inverting inputs (VIN+, VIN-, ...) are high-impedance CMOS inputs with low bias currents.
3.5
Exposed Thermal Pad (EP)
3.3
Power Supply Pins
There is an internal connection between the Exposed Thermal Pad (EP) and the VSS pin; they must be connected to the same potential on the Printed Circuit Board (PCB). This pad can be connected to a PCB ground plane to provide a larger heat sink. This improves the package thermal resistance (JA).
The positive power supply (VDD) is 1.8V to 5.5V higher than the negative power supply (VSS). For normal operation, the other pins are between VSS and VDD. Typically, these parts are used in a single (positive) supply configuration. In this case, VSS is connected to ground and VDD is connected to the supply. VDD will need bypass capacitors.
(c) 2008 Microchip Technology Inc.
DS22058C-page 19
MCP6V01/2/3
NOTES:
DS22058C-page 20
(c) 2008 Microchip Technology Inc.
MCP6V01/2/3
4.0 APPLICATIONS
4.1
The MCP6V01/2/3 family of auto-zeroed op amps is manufactured using Microchip's state of the art CMOS process. It is designed for low cost, low power and high precision applications. Its low supply voltage, low quiescent current and wide bandwidth makes the MCP6V01/2/3 ideal for battery-powered applications. VIN+ VIN- CFW Main Amp. NC VREF Null Input Switches 1 Null Output Switches Output Buffer
Overview of Auto-zeroing Operation
Figure 4-1 shows a simplified diagram of the MCP6V01/2/3 auto-zeroed op amps. This will be used to explain how the DC voltage errors are reduced in this architecture.
VOUT
CH
Null Amp.
POR Null Correct Switches 2
Oscillator
1 2
Digital Control
Clock Randomization
CS
FIGURE 4-1: 4.1.1
Simplified Auto-zeroed Op Amp Functional Diagram.
The internal POR ensures the part starts up in a known good state. It also provides protection against power supply brown out events. The Chip Select input places the op amp in a low power state when it is high. When it goes low, it powers the op amp at its normal level and starts operation properly. The Digital Control circuitry takes care of all of the housekeeping details of the switching operation. It also takes care of Chip Select and POR events.
BUILDING BLOCKS
The Null Amp. and Main Amp. are designed for high gain and accuracy using a differential topology. They have an auxiliary input (bottom left) used for correcting the offset voltages. Both inputs are added together internally. The capacitors at the auxiliary inputs (CFW and CH) hold the corrected values during normal operation. The Output Buffer is designed to drive external loads at the VOUT pin. It also produces a single ended output voltage (VREF is an internal reference voltage). All of these switches are make-before-break in order to minimize glitch-induced errors. They are driven by two clock phases (1 and 2) that select between normal mode and auto-zeroing mode. The clock is derived from an internal R-C oscillator running at a rate of fOSC1 = 300 kHz. The oscillator's output is divided down to the desired rate. It is also randomized to minimize (spread) undesired clock tones in the output.
(c) 2008 Microchip Technology Inc.
DS22058C-page 21
MCP6V01/2/3
4.1.2 AUTO-ZEROING ACTION
Figure 4-2 shows the connections between amplifiers during the Normal Mode of operation (1). The hold capacitor (CH) corrects the Null Amplifier's input offset. Since the Null Amplifier has very high gain, it dominates the signal seen by the Main Amplifier. This greatly reduces the impact of the Main Amplifier's input VIN+ VIN- CFW Null Amp. Main Amp. NC VREF Output Buffer offset voltage on overall performance. Essentially, the Null Amplifier and Main Amplifier behave as a regular op amp with very high gain (AOL) and very low offset voltage (VOS).
VOUT
CH
FIGURE 4-2:
Normal Mode of Operation (1); Equivalent Amplifier Diagram.
Since these corrections happen every 100 s, or so, we also minimize slow errors, including offset drift with temperature (VOS/TA), 1/f noise, and input offset aging.
Figure 4-3 shows the connections between amplifiers during the Auto-zeroing Mode of operation (2). The signal goes directly through the Main Amplifier, and the flywheel capacitor (CFW) maintains a constant correction on the Main Amplifier's offset. The Null Amplifier uses its own high open loop gain to drive the voltage across CH to the point where its input offset voltage is almost zero. Because the principal input is connected to VIN+, the auto-zeroing action corrects the offset at the current common mode input voltage (VCM) and supply voltage (VDD). This makes the DC CMRR and PSRR very high also. VIN+ VIN- CFW Null Amp.
Main Amp.
NC VREF
Output Buffer
VOUT
CH
FIGURE 4-3: 4.1.3
Auto-zeroing Mode of Operation (2); Equivalent Diagram.
response to produce IMD tones at sum and difference frequencies. IMD distortion tones are generated about all of the square wave clock's harmonics. Clock randomization spreads the IMD tones across the frequency spectrum, but cannot eliminate them. The spread energy is low and is not correlated with the signal of interest, so it is not of concern for most precision applications. See Figure 2-37 and Figure 2-38.
INTERMODULATION DISTORTION (IMD)
The MCP6V01/2/3 op amps will show intermodulation distortion (IMD), products when an AC signal is present. The signal and clock can be decomposed into sine wave tones (Fourier series components). These tones interact with the auto-zeroing circuitry's non-linear
DS22058C-page 22
(c) 2008 Microchip Technology Inc.
MCP6V01/2/3
4.2
4.2.1
Other Functional Blocks
RAIL-TO-RAIL INPUTS
The input stage of the MCP6V01/2/3 op amps uses two differential CMOS input stages in parallel. One operates at low common mode input voltage (VCM, which is approximately equal to VIN+ and VIN- in normal operation) and the other at high VCM. With this topology, the input operates with VCM up to 0.2V past either supply rail at +25C (see Figure 2-18). The input offset voltage (VOS) is measured at VCM = VSS - 0.2V and VDD + 0.2V to ensure proper operation. The transition between the input stages occurs when VCM VDD - 0.9V (see Figure 2-7 and Figure 2-8). For the best distortion and gain linearity, with non-inverting gains, avoid this region of operation.
pins (VIN+ and VIN-) from going too far above VDD, and dump any currents onto VDD. When implemented as shown, resistors R1 and R2 also limit the current through D1 and D2. VDD D1 V1 R1 V2 R2 VSS - (minimum expected V1) 2 mA VSS - (minimum expected V2) R2 > 2 mA R1 > D2 MCP6V0X VOUT
4.2.1.1
Phase Reversal
The input devices are designed to not exhibit phase inversion when the input pins exceed the supply voltages. Figure 2-43 shows an input voltage exceeding both supplies with no phase inversion.
FIGURE 4-5: Inputs.
Protecting the Analog
4.2.1.2
Input Voltage and Current Limits
The ESD protection on the inputs can be depicted as shown in Figure 4-4. This structure was chosen to protect the input transistors, and to minimize input bias current (IB). The input ESD diodes clamp the inputs when they try to go more than one diode drop below VSS. They also clamp any voltages that go too far above VDD; their breakdown voltage is high enough to allow normal operation, and low enough to bypass quick ESD events within the specified limits. VDD Bond Pad
It is also possible to connect the diodes to the left of the resistor R1 and R2. In this case, the currents through the diodes D1 and D2 need to be limited by some other mechanism. The resistors then serve as in-rush current limiters; the DC current into the input pins (VIN+ and VIN-) should be very small. A significant amount of current can flow out of the inputs (through the ESD diodes) when the common mode voltage (VCM) is below ground (VSS); see Figure 2-17. Applications that are high impedance may need to limit the usable voltage range.
4.2.2
RAIL-TO-RAIL OUTPUT
VIN+ Bond Pad
Input Stage
Bond V - IN Pad
The output voltage range of the MCP6V01/2/3 auto-zeroed op amps is VDD - 15 mV (minimum) and VSS + 15 mV (maximum) when RL = 20 k is connected to VDD/2 and VDD = 5.5V. Refer to Figure 2-19 and Figure 2-20 for more information. These op amps are designed to drive light loads; use another amplifier to buffer the output from heavy loads.
VSS Bond Pad
4.2.3
CHIP SELECT (CS)
FIGURE 4-4: Structures.
Simplified Analog Input ESD
In order to prevent damage and/or improper operation of these amplifiers, the circuit must limit the currents (and voltages) at the input pins (see Section 1.1 "Absolute Maximum Ratings "). Figure 4-5 shows the recommended approach to protecting these inputs. The internal ESD diodes prevent the input pins (VIN+ and VIN-) from going too far below ground, and the resistors R1 and R2 limit the possible current drawn out of the input pins. Diodes D1 and D2 prevent the input
The single MCP6V03 has a Chip Select (CS) pin. When CS is pulled high, the supply current for the corresponding op amp drops to about 1 A (typical), and is pulled through the CS pin to VSS. When this happens, the amplifier is put into a high impedance state. By pulling CS low, the amplifier is enabled. If the CS pin is left floating, the internal pull-down resistor (about 5 M) will keep the part on. Figure 1-4 shows the output voltage and supply current response to a CS pulse.
(c) 2008 Microchip Technology Inc.
DS22058C-page 23
MCP6V01/2/3
4.3
4.3.1
Application Tips
INPUT OFFSET VOLTAGE OVER TEMPERATURE
4.3.4
SOURCE CAPACITANCE
Table 1-1 gives both the linear and quadratic temperature coefficients (TC1 and TC2) of input offset voltage. The input offset voltage, at any temperature in the specified range, can be calculated as follows:
The capacitances seen by the two inputs should be small and matched. The internal switches connected to the inputs dump charges on these capacitors; an offset can be created if the capacitances do not match.
4.3.5
CAPACITIVE LOADS
EQUATION 4-1:
V OS ( T A ) = V OS + TC 1 T + TC 2 T Where: T VOS(TA) VOS TC1 TC2 = = = = = TA - 25C input offset voltage at TA input offset voltage at +25C linear temperature coefficient quadratic temperature coefficient
2
Driving large capacitive loads can cause stability problems for voltage feedback op amps. As the load capacitance increases, the feedback loop's phase margin decreases and the closed-loop bandwidth is reduced. This produces gain peaking in the frequency response, with overshoot and ringing in the step response. These auto-zeroed op amps have a different output impedance than most op amps, due to their unique topology. When driving a capacitive load with these op amps, a series resistor at the output (RISO in Figure 4-6) improves the feedback loop's phase margin (stability) by making the output load resistive at higher frequencies. The bandwidth will be generally lower than the bandwidth with no capacitive load. RISO VOUT CL MCP6V0X
4.3.2
DC GAIN PLOTS
Figure 2-9, Figure 2-10 and Figure 2-11 are histograms of the reciprocals (in units of V/V) of CMRR, PSRR and AOL, respectively. They represent the change in input offset voltage (VOS) with a change in common mode input voltage (VCM), power supply voltage (VDD) and output voltage (VOUT). The 1/AOL histogram is centered near 0 V/V because the measurements are dominated by the op amp's input noise. The negative values shown represent noise, not unstable behavior. We validate the op amps' stability by making multiple measurements of VOS; instability would manifest itself as a greater unexplained variability in VOS or as the railing of the output.
FIGURE 4-6: Output Resistor, RISO, Stabilizes Capacitive Loads.
Figure 4-7 gives recommended RISO values for different capacitive loads and is independent of the gain.
10000 10k Recommended R ISO ()
4.3.3
SOURCE RESISTANCES
The input bias currents have two significant components; switching glitches that dominate at room temperature and below, and input ESD diode leakage currents that dominate at +85C and above. Make the resistances seen by the inputs small and equal. This minimizes the output offset caused by the input bias currents. The inputs should see a resistance on the order of 10 to 1 k at high frequencies (i.e., above 1 MHz). This helps minimize the impact of switching glitches, which are very fast, on overall performance. In some cases, it may be necessary to add resistors in series with the inputs to achieve this improvement in performance.
1k 1000
GN < 2
100 100
GN = 5 GN = 10
10 10 1p 1.E-12
10p 1.E-11
100p 1n 1.E-10 1.E-09 CL (F)
10n 1.E-08
100n 1.E-07
FIGURE 4-7: Recommended RISO values for Capacitive Loads.
DS22058C-page 24
(c) 2008 Microchip Technology Inc.
MCP6V01/2/3
After selecting RISO for your circuit, double check the resulting frequency response peaking and step response overshoot. Modify RISO's value until the response is reasonable. Bench evaluation and simulations with the MCP6V01 SPICE macro model (good for all of the MCP6V01/2/3 op amps) are helpful.
4.3.7
REDUCING UNDESIRED NOISE AND SIGNALS
Reduce undesired noise and signals with: * Low bandwidth signal filters: - Minimizes random analog noise - Reduces interfering signals * Good PCB layout techniques: - Minimizes crosstalk - Minimizes parasitic capacitances and inductances that interact with fast switching edges * Good power supply design: - Isolation from other parts - Filtering of interference on supply line(s)
4.3.6
STABILIZING OUTPUT LOADS
This family of auto-zeroed op amps has an output impedance (Figure 2-31 and Figure 2-32) that has a double zero when the gain is low. This can cause a large phase shift in feedback networks that have low resistance near the part's bandwidth. This large phase shift can cause stability problems. Figure 4-8 shows one circuit example that has low resistance near the part's bandwidth. RF and CF set a pole at 0.16 kHz, so the noise gain (GN) is 1 V/V at the circuit's bandwidth (roughly 1.3 MHz). The load seen by the op amp's output at 1.3 MHz is RG||RL (99). This is low enough to be a real concern. VIN
4.3.8
SUPPLY BYPASSING AND FILTERING
RN 100
With this family of operational amplifiers, the power supply pin (VDD for single supply) should have a local bypass capacitor (i.e., 0.01 F to 0.1 F) within 2 mm of the pin for good high-frequency performance. These parts also need a bulk capacitor (i.e., 1 F or larger) within 100 mm to provide large, slow currents. This bulk capacitor can be shared with other low noise, analog parts. Additional filtering of high frequency power supply noise (e.g., switched mode power supplies) can be achieved using resistors. The resistors need to be small enough to prevent a large drop in VDD for the op amp, which would cause a reduced output range and possible load-induced power supply noise. The resistors also need to be large enough to dissipate little power when VDD is turned on and off quickly. The circuit in Figure 4-10 gives good rejection out to 1 MHz for switched mode power supplies. Smaller resistors and capacitors are a better choice for designs where the power supply is reasonably quiet. VS_ANA
MCP6V0X
VOUT RL 10.0 k
RG 100
RF 10.0 k CF 0.1 F
FIGURE 4-8:
Output Load Issue.
To solve this problem, increase the resistive load to at least 3 k. Methods to accomplish this task include: * Increase RG * Remove CF (relocate the filter) * Add a 3 k resistor at the op amp's output that is not in the signal path; see Figure 4-9 VIN
RN 100
MCP6V0X RX 3.01 k RF 10.0 k CF 0.1 F VOUT RL 10.0 k
143 1/4W 100 F
143 1/10W 100 F 0.1 F MCP6V0X
RG 100
to other analog parts
FIGURE 4-10:
Additional Supply Filtering.
FIGURE 4-9: Load Issue.
One Solution To Output
(c) 2008 Microchip Technology Inc.
DS22058C-page 25
MCP6V01/2/3
4.3.9 PCB DESIGN FOR DC PRECISION 4.3.9.2
In order to achieve DC precision on the order of 1 V, many physical errors need to be minimized. The design of the Printed Circuit Board (PCB), the wiring, and the thermal environment has a strong impact on the precision achieved. A poor PCB design can easily be more than 100 times worse than the MCP6V01/2/3 op amps minimum and maximum specifications.
Non-inverting and Inverting Amplifier Layout for Thermo-junctions
Figure 4-11 shows the recommended non-inverting and inverting gain amplifier circuits on one schematic. Usually, to minimize the input bias current related offset, R1 is chosen to be R2||R3. The guard traces (with ground vias at the ends) help minimize the thermal gradients. The resistor layout cancels the resistor thermal voltages, assuming the temperature gradient is constant near the resistors:
4.3.9.1
Thermo-junctions
Any time two dissimilar metals are joined together, a temperature dependent voltage appears across the junction (the Seebeck or thermo-junction effect). This effect is used in thermocouples to measure temperature. The following are examples of thermo-junctions on a PCB: * Components (resistors, op amps, ...) soldered to a copper pad * Wires mechanically attached to the PCB * Jumpers * Solder joints * PCB vias Typical thermo-junctions have temperature to voltage conversion coefficients of 10 to 100 V/C (sometimes higher). There are three basic approaches to minimizing thermo-junction effects: * Minimize thermal gradients * Cancel thermo-junction voltages * Minimize difference in thermal potential between metals
EQUATION 4-2:
VOUT VPGP, -VMGM, Where: GM GP = = R3/R2, inverting gain magnitude 1 + GM, non-inverting gain magnitude VOS is neglected VM = GND VP = GND
VM VP
R3 R2 R1
U1
VOUT
R2 VM U1 MCP6V01 VP R1
R3
VOUT
FIGURE 4-11: PCB Layout and Schematic for Single Non-inverting and Inverting Amplifiers.
Note: Changing the orientation of the resistors will usually cause a significant decrease in the cancellation of the thermal voltages.
DS22058C-page 26
(c) 2008 Microchip Technology Inc.
MCP6V01/2/3
4.3.9.3 Difference Amplifier Layout for Thermo-junctions 4.3.9.4 Dual Non-inverting Amplifier Layout for Thermo-junctions
Figure 4-12 shows the recommended difference amplifier circuit. Usually, we choose R1 = R2 and R3 = R4. The guard traces (with ground vias at the ends) help minimize the thermal gradients. The resistor layout cancels the resistor thermal voltages, assuming the temperature gradient is constant near the resistors: The dual op amp amplifiers shown in Figure 4-16 and Figure 4-17 produce a non-inverting difference gain greater than 1, and a common mode gain of 1 .They can use the layout shown in Figure 4-13. The gain setting resistors (R2) between the two sides are not combined so that the thermal voltages can be canceled. The guard traces (with ground vias at the ends) help minimize the thermal gradients. The resistor layout cancels the resistor thermal voltages, assuming the temperature gradient is constant near the resistors:
EQUATION 4-3:
VOUT VREF + (VP - VM)GDM Where: Thermal voltages are approximately equal GDM = R3/R1 = R4/R2, difference gain VOS is neglected
EQUATION 4-4:
(VOA - VOB) (VIA - VIB)GDM (VOA + VOB)/2 (VIA + VIB)/2
Where: GDM GCM
Thermal voltages are approximately equal = = R4 R2 R1 R3 VOUT 1 + R3/R2, differential mode gain 1, common mode gain VOS is neglected
U1
VM VP
VREF R4 VOUT VREF R3 R2 R1
VOA U1
VOB R3 R2 R1
R2 VM U1 MCP6V01 VP R1
R3
VIA VIA R1 1/2 MCP6V02 U1 R2 R2 U1 1/2 MCP6V02 VIB R1
VIB
FIGURE 4-12: PCB Layout and Schematic for Single Difference Amplifier.
Note: Changing the orientation of the resistors will usually cause a significant decrease in the cancellation of the thermal voltages.
VOA
R3 R3
VOB
FIGURE 4-13: PCB Layout and Schematic for Dual Non-inverting Amplifier.
Note: Changing the orientation of the resistors will usually cause a significant decrease in the cancellation of the thermal voltages.
(c) 2008 Microchip Technology Inc.
DS22058C-page 27
MCP6V01/2/3
4.3.9.5 Other PCB Thermal Design Tips 4.3.9.6 Crosstalk
In cases where an individual resistor needs to have its thermo-junction voltage cancelled, it can be split into two equal resistors as shown in Figure 4-14. To keep the thermal gradients near the resistors as small as possible, the layouts are symmetrical with a ring of metal around the outside. Make R1A = R1B = R1/2 and R2A = R2B = 2R2. R1A R1B R2A DC crosstalk causes offsets that appear as a larger input offset voltage. Common causes include: * Common mode noise (remote sensors) * Ground loops (current return paths) * Power supply coupling Interference from the mains (usually 50 Hz or 60 Hz), and other AC sources, can also affect the DC performance. Non-linear distortion can convert these signals to multiple tones, included a DC shift in voltage. When the signal is sampled by an ADC, these AC signals can also be aliased to DC, causing an apparent shift in offset. To reduce interference: Keep traces and wires as short as possible Use shielding (e.g., encapsulant) Use ground plane (at least a star ground) Place the input signal source near to the DUT Use good PCB layout techniques Use a separate power supply filter (bypass capacitors) for these auto-zeroed op amps
R2B R1A R1B R2A
R2B
FIGURE 4-14: Resistors.
Note:
PCB Layout for Individual
Changing the orientation of the resistors will usually cause a significant decrease in the cancellation of the thermal voltages.
4.3.9.7
Miscellaneous Effects
Minimize temperature gradients at critical components (resistors, op amps, heat sources, etc.): * Minimize exposure to gradients - Small components - Tight spacing - Shield from air currents * Align with constant temperature (contour) lines - Place on PCB center line * Minimize magnitude of gradients - Select parts with lower power dissipation - Use same metal junctions on thermo-junctions that need to match - Use metal junctions with low temperature to voltage coefficients - Large distance from heat sources - Ground plane underneath (large area) - FR4 gaps (no copper for thermal insulation) - Series resistors inserted into traces (adds thermal and electrical resistance) - Use heat sinks Make the temperature gradient point in one direction: * Add guard traces - Constant temperature curves follow the traces - Connect to ground plane * Shape any FR4 gaps - Constant temperature curves follow the edges
Keep the resistances seen by the input pins as small and as near to equal as possible to minimize bias current related offsets. Make the (trace) capacitances seen by the input pins small and equal. This is helpful in minimizing switching glitch-induced offset voltages. Bending a coax cable with a radius that is too small causes a small voltage drop to appear on the center or (the tribo-electric effect). Make sure the bending radius is large enough to keep the conductors and insulation in full contact. Mechanical stresses can make some capacitor types (such as ceramic) to output small voltages. Use more appropriate capacitor types in the signal path and minimize mechanical stresses and vibration. Humidity can cause electro-chemical potential voltages to appear in a circuit. Proper PCB cleaning helps, as does the use of encapsulants.
DS22058C-page 28
(c) 2008 Microchip Technology Inc.
MCP6V01/2/3
4.4
4.4.1
Typical Applications
WHEATSTONE BRIDGE
4.4.2
RTD SENSOR
Many sensors are configured as Wheatstone bridges. Strain gauges and pressure sensors are two common examples. These signals can be small and the common mode noise large. Amplifier designs with high differential gain are desirable. Figure 4-15 shows how to interface to a Wheatstone bridge with a minimum of components. Because the circuit is not symmetric, the ADC input is single ended, and there is a minimum of filtering, the CMRR is good enough for moderate common mode noise. VDD R R 0.2R 0.2R MCP6V01 0.01C 100R 3 k VDD ADC
The ratiometric circuit in Figure 4-17 conditions a three wire RTD. It corrects for the sensor's wiring resistance by subtracting the voltage across the middle RW. The top R1 does not change the output voltage; it balances the op amp inputs. Failure (open) of the RTD is detected by an out of range voltage. 1/2 MCP6V02 2.49 k VDD RW RT 20 k 10 nF RRTD 100 R1 2.49 k 1 F 10 nF R1 2.49 k 100 nF R3 100 k R2 2.55 k R2 2.55 k R3 100 k 100 nF 2.49 k 1/2 MCP6V02 3 k
3 k VDD ADC
R
R
FIGURE 4-15:
Simple Design.
RW RW
Figure 4-16 shows a higher performance circuit for Wheatstone bridges. This circuit is symmetric and has high CMRR. Using a differential input to the ADC helps with the CMRR. 1/2 MCP6V02 200 VDD RR 10 nF 200 RR 1 F 200 10 nF 3 k 20 k 1 F 200 1/2 MCP6V02 1 F 20 k 3 k VDD ADC
RB 20 k
FIGURE 4-17:
RTD Sensor.
The voltages at the input of the ADC can be calculated with the following: G RTD = 1 + 2 R 3 R 2 G W = G RTD - R 3 R 1 V DM = G RTD ( V T - V B ) + G W V W V T + V B + ( G RTD + 1 - G W )V W V CM = -----------------------------------------------------------------------------2 Where: VT VB VW VCM VDM = = = = = Voltage at the top of RRTD Voltage at the bottom of RRTD Voltage across top and middle RW's ADC's common mode input ADC's differential mode input
FIGURE 4-16:
High Performance Design.
(c) 2008 Microchip Technology Inc.
DS22058C-page 29
MCP6V01/2/3
4.4.3 THERMOCOUPLE SENSOR
Figure 4-18 shows a simplified diagram of an amplifier and temperature sensor used in a thermocouple application. The type K thermocouple senses the temperature at the hot junction (THJ), and produces a voltage at V1 proportional to THJ (in C). The amplifier's gain is is set so that V4/THJ is 10 mV/C. V3 represents the output of a temperature sensor, which produces a voltage proportional to the temperature (in C) at the cold junction (TCJ), and with a 0.50V offset. V2 is set so that V4 is 0.50V when THJ - TCJ is 0C. The MCP9700A senses the temperature at its physical location. It needs to be at the same temperature as the cold junction (TCJ), and produces V3 (Figure 4-16). The MCP1541 produces a 4.10V output, assuming VDD is at 5.0V. This voltage, tied to a resistor ladder of 4.100(RTH) and 1.3224(RTH), would produce a Thevenin equivalent of 1.00V and 250(RTH). The 1.3224(RTH) resistor is combined in parallel with the top right RTH resistor (in Figure 4-18), producing the 0.5696(RTH) resistor. V4 should be converted to digital, then corrected for the thermocouple's non-linearity. The ADC can use the MCP1541 as its voltage reference. Alternately, an absolute reference inside a PICmicro(R) can be used instead of the MCP1541.
EQUATION 4-5:
V1 THJ(40 V/C) V2 = (1.00V) V3 = TCJ(10 mV/C) + (0.50V) V4 = 250V1 + (V2 - V3) (10 mV/C) (THJ - TCJ) + (0.50V) (hot junction RTH = Thevenin Equivalent Resistance at THJ) (R ) (R ) V2 40 V/C Type K Thermocouple (RTH)/250 V1 (cold junction at TCJ) (RTH)/250 V3 (RTH) C (RTH)
TH TH
4.4.4
OFFSET VOLTAGE CORRECTION
Figure 4-20 shows a MCP6V01 correcting the input offset voltage of another op amp. R2 and C2 integrate the offset error seen at the other op amp's input; the integration needs to be slow enough to be stable (with the feedback provided by R1 and R3). R1 R2 C2 3 k MCP6V01 MCP6XXX R3
C MCP6V01 V4
VIN
VOUT
R2 VDD/2
FIGURE 4-20: 4.4.5
Offset Correction.
FIGURE 4-18: Simplified Circuit.
Thermocouple Sensor;
PRECISION COMPARATOR
Figure 4-19 shows a more complete implementation of this circuit. The dashed red arrow indicates a thermally conductive connection between the thermocouple and the MCP9700A; it needs to be very short and have low thermal resistance. RTH = Thevenin Equivalent Resistance (e.g.: 10 k) VDD 4.100(RTH) 0.5696(RTH) MCP1541 C Type K V1 VDD MCP9700A (RTH) (RTH)/250 C (RTH) 3 k V4 (RTH)/250 MCP6V01
Use high gain before a comparator to improve the latter's performance. Do not use MCP6V01/2/3 as a comparator by itself; the VOS correction circuitry does not operate properly without a feedback loop. MCP6V01 VIN R1 R3 R4
R2 VDD/2
R5
1 k VOUT
MCP6541
FIGURE 4-21:
Precision Comparator.
FIGURE 4-19:
Thermocouple Sensor.
DS22058C-page 30
(c) 2008 Microchip Technology Inc.
MCP6V01/2/3
5.0 DESIGN AIDS
5.5
Microchip provides the basic design aids needed for the MCP6V01/2/3 family of op amps.
Analog Demonstration and Evaluation Boards
5.1
SPICE Macro Model
The latest SPICE macro model for the MCP6V01/2/3 op amps is available on the Microchip web site at www.microchip.com. This model is intended to be an initial design tool that works well in the op amp's linear region of operation over the temperature range. See the model file for information on its capabilities. Bench testing is a very important part of any design and cannot be replaced with simulations. Also, simulation results using this macro model need to be validated by comparing them to the data sheet specifications and characteristic curves.
Microchip offers a broad spectrum of Analog Demonstration and Evaluation Boards that are designed to help customers achieve faster time to market. For a complete listing of these boards and their corresponding user's guides and technical information, visit the Microchip web site at www.microchip.com/analog tools. Some boards that are especially useful are: * MCP6V01 Thermocouple Auto-Zeroed Reference Design * MCP6XXX Amplifier Evaluation Board 1 * MCP6XXX Amplifier Evaluation Board 2 * MCP6XXX Amplifier Evaluation Board 3 * MCP6XXX Amplifier Evaluation Board 4 * Active Filter Demo Board Kit * P/N SOIC8EV: 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board * P/N SOIC14EV: 14-Pin SOIC/TSSOP/DIP Evaluation Board
5.2
FilterLab(R) Software
Microchip's FilterLab(R) software is an innovative software tool that simplifies analog active filter (using op amps) design. Available at no cost from the Microchip web site at www.microchip.com/filterlab, the Filter-Lab design tool provides full schematic diagrams of the filter circuit with component values. It also outputs the filter circuit in SPICE format, which can be used with the macro model to simulate actual filter performance.
5.6
Application Notes
The following Microchip Application Notes are available on the Microchip web site at www.microchip. com/appnotes and are recommended as supplemental reference resources. ADN003: "Select the Right Operational Amplifier for your Filtering Circuits", DS21821 AN722: "Operational Amplifier Topologies and DC Specifications", DS00722 AN723: "Operational Amplifier AC Specifications and Applications", DS00723 AN884: "Driving Capacitive Loads With Op Amps", DS00884 AN990: "Analog Sensor Conditioning Circuits - An Overview", DS00990 These application notes and others are listed in the design guide: "Signal Chain Design Guide", DS21825
5.3
MindiTM Circuit Designer & Simulator
Microchip's MindiTM Circuit Designer & Simulator aids in the design of various circuits useful for active filter, amplifier and power management applications. It is a free online circuit designer & simulator available from the Microchip web site at www.microchip.com/mindi. This interactive circuit designer & simulator enables designers to quickly generate circuit diagrams, and simulate circuits. Circuits developed using the Mindi Circuit Designer & Simulator can be downloaded to a personal computer or workstation.
5.4
Microchip Advanced Part Selector (MAPS)
MAPS is a software tool that helps efficiently identify Microchip devices that fit a particular design requirement. Available at no cost from the Microchip website at www.microchip.com/maps, the MAPS is an overall selection tool for Microchip's product portfolio that includes Analog, Memory, MCUs and DSCs. Using this tool, a customer can define a filter to sort features for a parametric search of devices and export side-by-side technical comparison reports. Helpful links are also provided for Data sheets, Purchase and Sampling of Microchip parts.
(c) 2008 Microchip Technology Inc.
DS22058C-page 31
MCP6V01/2/3
NOTES:
DS22058C-page 32
(c) 2008 Microchip Technology Inc.
MCP6V01/2/3
6.0
6.1
PACKAGING INFORMATION
Package Marking Information
8-Lead DFN (4x4) (MCP6V02)
Example
XXXXXX XXXXXX YYWW NNN
8-Lead SOIC (150 mil) XXXXXXXX XXXXYYWW NNN
6V02 e3 E/MD^^ 0750 256
Example:
MCP6VO1E SN e3 0750 256
8-Lead TDFN (2x3) (MCP6V01, MCP6V03)
Device MCP6V01 MCP6V03 Code AAA AAB
Example:
XXX YWW NN
AAA 838 25
Note: Applies to 8-Lead 2x3 TDFN
Legend: XX...X Y YY WW NNN * Note:
e3
Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
(c) 2008 Microchip Technology Inc.
DS22058C-page 33
MCP6V01/2/3
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DS22058C-page 35
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DS22058C-page 36
(c) 2008 Microchip Technology Inc.
MCP6V01/2/3
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DS22058C-page 37
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DS22058C-page 38
(c) 2008 Microchip Technology Inc.
MCP6V01/2/3
APPENDIX A: REVISION HISTORY
Revision C (December 2008)
The following is the list of modifications: 1. 2. 3. 4. Added the 8-lead, 2x3 TDFN package for the MCP6V01 and MCP6V03 devices. Corrected the IMD specification in Table 1-2. Added 8-lead, 2x3 TDFN package information to Thermal Characteristic table. Added information on the Exposed Thermal Pad (EP) for the 8-lead, 2x3 TDFN and 8-lead, 4x4 DFN packages. Added Section 4.3.6 "Stabilizing Output Loads" Other minor typographical corrections.
5. 6.
Revision B (June 2008)
The following is the list of modifications: 1. 2. 3. 4. 5. 6. 7. 8. Updated the specifications and their conditions. Corrected the Timing Diagrams. Added to the Test Circuits. Added RISO (see Figure 4-6) to all circuit diagrams. Added the Typical Performance Curves. Corrected and expanded Applications Information. Minor edits due to change in production status. Added Appendix B, Offset Related Test Screens.
Revision A (September 2007)
* Original Release of this Document.
(c) 2008 Microchip Technology Inc.
DS22058C-page 41
MCP6V01/2/3
APPENDIX B: OFFSET RELATED TEST SCREENS
We use production screens to ensure the quality of our outgoing products. These screens are set at wider limits to eliminate any fliers; see Table B-1.
Input offset voltage related specifications in the DC spec table (Table 1-1) are based on bench measurements (see Section 2.1 "DC Input Precision"). These measurements are much more accurate because: * * * * More compact circuit Soldered parts on the PCB More time spent averaging (reduces noise) Better temperature control - Reduced temperature gradients - Greater accuracy
TABLE B-1:
OFFSET RELATED TEST SCREENS
Electrical Characteristics: Unless otherwise indicated, TA = 25C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 20 k to VL, and CS = GND (refer to Figure 1-5 and Figure 1-6).
Parameters
Input Offset Input Offset Voltage Input Offset Voltage Drift with Temperature (linear Temp. Co.) Power Supply Rejection Common Mode Common Mode Rejection Open-Loop Gain DC Open-Loop Gain (large signal) Note 1: 2: 3:
Sym
VOS TC1 PSRR CMRR CMRR AOL AOL
Min
-10 -- 115 106 116 114 122
Max
+10 -- -- -- -- -- --
Units
V
Conditions
TA = +25C (Note 1, Note 2)
nV/C TA = -40 to +125C (Note 3) dB dB dB dB dB (Note 1) VDD = 1.8V, VCM = -0.2V to 2.0V (Note 1) VDD = 5.5V, VCM = -0.2V to 5.7V (Note 1) VDD = 1.8V, VOUT = 0.2V to 1.6V (Note 1) VDD = 5.5V, VOUT = 0.2V to 5.3V (Note 1)
Due to thermal junctions and other errors in the production environment, these specifications are only screened in production. VOS is also sample screened at +125C. TC1 is not measured in production.
DS22058C-page 42
(c) 2008 Microchip Technology Inc.
MCP6V01/2/3
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device -X Temperature Range /XXX Package Examples:
a) b) a) b) MCP6V01T-E/SN: Extended temperature, 8LD SOIC package. MCP6V01-E/MNY:Extended temperature, 8LD 2x3 TDFN package. MCP6V02-E/MD: Extended temperature, 8LD 4x4 DFN package. MCP6V02T-E/SN: Tape and Reel, Extended temperature, 8LD SOIC package. MCP6V03-E/SN: Extended temperature, 8LD SOIC package. MCP6V03-E/MNY:Extended temperature, 8LD 2x3 TDFN package.
Device:
MCP6V01 Single Op Amp MCP6V01T Single Op Amp (Tape and Reel for 2x3 TDFN andSOIC) MCP6V02 Dual Op Amp MCP6V02T Dual Op Amp (Tape and Reel for 4x4 DFN and SOIC) MCP6V03 Single Op Amp with Chip Select MCP6V03T Single Op Amp with Chip Select (Tape and Reel for SOIC) E MD = -40C to +125C
a) b)
Temperature Range: Package:
= Plastic Dual Flat, No-Lead (4x4x0.9 mm), 8-lead (MCP6V02 only) MNY * = Plastic Dual Flat No Lead (2x3x0.75 mm), 8-lead (MCP6V01, MCP6V03) SN = Plastic SOIC (150mil Body), 8-lead * Y = nickel palladium gold manufacturing designator. Only available on the TDFN package.
(c) 2008 Microchip Technology Inc.
DS22058C-page 43
MCP6V01/2/3
NOTES:
DS22058C-page 44
(c) 2008 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: * * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC, SmartShunt and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2008, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
(c) 2008 Microchip Technology Inc.
DS22058C-page 45
WORLDWIDE SALES AND SERVICE
AMERICAS
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ASIA/PACIFIC
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01/02/08
DS22058C-page 46
(c) 2008 Microchip Technology Inc.

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